View HIP0051_138014.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HIP0051
June 1996
0.25A/50V Octal Low Side Power Driver with Serial Bus Control
Description
The HIP0051 is a logic controlled, eight channel Octal Low Side Power Driver. As shown in the Block Diagram, the outputs are controlled via the serial data interface which allows the data to be shifted out, allowing control of other cascaded serial devices. The HIP0051 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. It is particularly suited for driving lamps, displays, relays, and solenoids in applications where low operating power, high breakdown voltage, and high output current at high temperature is required.
Features
* Eight Open Drain - NDMOS Low Side Drivers Each Capable of 250mA * High Voltage Power BiMOS with Low Idle and Standby Current * Over-Voltage Clamp Protection - Each Output . . . . . . . . . . . . . . . . . . . . . . . 50V Typical * Serial Data Input, Parallel Output Power Drive * Common Enable for Output Drivers and Data Storage Register * -40oC to 85oC Operating Range
Applications
* Automotive and Industrial Systems * Solenoids, Relays and Lamp Drivers * Logic and P Controlled Drivers * Robotic Controls
Ordering Information
PART NUMBER HIP0051IB TEMP. RANGE (oC) -40 to 85 PACKAGE 20 Ld SOIC PKG. NO. M20.3
Pinout
HIP0051 (SOIC) TOP VIEW
GND VCC SI DR0 DR1 DR2 DR3 NC EN 1 2 3 4 5 6 7 8 9 20 GND 19 LGND 18 SO 17 DR7 16 DR6 15 DR5 14 DR4 13 SCK 12 STR 11 GND
Block Diagram
(ENABLE) (STROBE) Q0 SI 8-BIT SERIAL (SPI) INPUT REGISTER (DATA IS PARALLEL OUTPUT LATCHED WHEN STROBED) Q1 Q2 Q3 Q4 Q5 Q6 Q7 OUTPUT DRIVER (CHANNEL 1 OF 8) DR#0
EN STR
OUTPUT LATCH
SCK
GND 10
SO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4155
1
Specifications HIP0051
Absolute Maximum Ratings
Output Voltage, VOUT (Note 1). . . . . . . . . . . . . . . . . . . -0.3V to 40V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Output Clamp Energy, 25oC (5ms Pulse). . . . . . . . . . . . . . . . . 75mJ Continuous Output Load Current, ILOAD (Each Output) . . . . . 0.25A Continuous Output Current, ILOAD (All Outputs ON, Note 2). . 1.69A Peak Output Current Each Output, Other Outputs OFF . . . . . . . . . . . . . . . . . . . . . 2A Peak Avalanche Current (3ms duration) . . . . . . . . . . . . . . . . . . 1A
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC Lead Tips Only)
Operating Conditions
Operating Ambient Temperature Range, TA . . . . . . . -40oC to 85oC Operating Logic Supply Voltage Range, VCC . . . . . +4.5V to +5.5V Power Output Driver Voltage Range. . . . . . . . . . . . . . . . . . 0 to VOC Max. Supply Current, with 100mA each Output . . . . . . . . . . . 100A Max. Supply Current, with No Load, Outputs OFF . . . . . . . . . 100A Logic Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7xVCC Logic Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2xVCC Typical Output RDSON Channel Resistance. . . . . . . . . . . . . . . . . 2 Typical Output Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4s Typical Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10s
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the Output Clamp voltage VOC. 2. The maximum continuous current with all outputs on is limited by package dissipation. At 25oC ambient temperature, the maximum equal current with all outputs ON is 211mA in each output for a total of 1.69A. At a maximum ambient temperature of TA = 85oC and rDSON(Max) = 3.5, each output is limited to 152mA and the total current for all 8 outputs ON is 8 x 152mA = 1.22A. 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OUTPUTS DRIVERS (DR0 TO DR7) Output Channel Resistance Output Clamping Voltage Output Clamping Energy Peak Output Load Currents, Short Duration Cold Start-up Lamp Currents Output OFF Leakage Current Output Rise Time Output Fall Time Output Delay from Strobe, High to Low Output Transition Output Delay from Strobe, Low to High Output Transition LOGIC SUPPLY Logic Supply Current, Loaded Logic Supply Current, No Load ICC ICC All Outputs ON, 200mA Load at each Output All Outputs OFF 100 100 A A rDS(ON) VOC EOC IPEAK ILAMP IOFF trise tfall tDHL tDLH Output Current = 200mA, TA = 85oC Outputs OFF 5ms Pulse, TA = 25oC 100s Duration, Each Output, all Outputs ON, Duty Cycle 2% 5ms Duration, Each Output, all Outputs ON, Duty Cycle 17% Output Voltage = 40V, TA = 85oC Load = 75, 0.01F (RC in Parallel), VBATT = 18V 42 75 0.85 0.3 0.5 0.5 1 0.2 2 50 190 -0.2 4 10 4 2.6 10 30 30 10 10 3.5 58 V mJ A A A s s s s
2
Specifications HIP0051
Electrical Specifications
PARAMETER LOGIC INPUTS (EN, SI, SCK, STR) Threshold Voltage at Falling Edge Threshold Voltage at Rising Edge Hysteresis Voltage Leakage Current Leakage Current SERIAL DATA CLOCK (SCK) Frequency Pulse Width High Pulse Width Low SERIAL DATA IN (SI) Input Setup Time Input Hold Time STROBE (STR) Strobe Pulse Width Min. Clock to Strobe Delay SERIAL DATA OUT (SO) Low Level Output Voltage High Level Output Voltage Propagation Delay VOL VOH tP(CD) Sink Current = 1.6mA Source Current = -1.6mA 3.7 75 0.2 4.4 260 0.4 V V ns tW(S) tD(CS) 150 75 12 5 ns ns tSUI THI 1.1 1.5 75 75 ns ns fSCK tW(CKH) tW(CKL) 175 175 27 27 1.6 MHz ns ns VTVT+ VH I LIN I LIN VCC = 5V 10% VCC = 5V 10% VT+ - VTVCC = 5V VCC = 0V 0.2VCC 0.85 -10 -10 0.3VCC 0.6VCC 1.4 -0.2 -0.1 0.7VCC 2.25 10 10 V V V A A VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC, Unless Otherwise Specified. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
tW(SCK) SCK (CLOCK) tSUI SI (SERIAL DATA IN)
tW(SCK)
tHI
tD(CS) STR (STROBE) tDHL tDLH DRx (POWER OUTPUT DRIVER) tP(CD) SO (SERIAL DATA OUT)
tW(S)
90% 10% tfall, trise
FIGURE 1. LOGIC TIMING CONTROL SPECIFICATIONS
3
HIP0051 Pin Descriptions
VCC - Logic Power Supply The VCC pin is the positive 5V logic voltage supply input for the IC. The normal operating voltage range is 4.5 to 5.5V. When switched on, the POR forces all outputs off. SCK - Serial Clock SCK is the clock input for the SPI interface. Output ON/OFF control data is clocked into an eight stage shift register on the rising edge of an external clock. This input has a Schmitt trigger. SI - Serial Data In SI is the Serial Data Input pin for the SPI interface. The eight Power Outputs are controlled by the serial data via the Output Data Buffer. This input has a Schmitt trigger. STR - Strobe for the SPI Interface When the STR pin is high, data from the 8-bit shift register is passed into the Output Data Buffers where it controls the ON-OFF state of each output driver. The data is latched in the Output Data Buffers on the trailing edge of the STR pulse. This input has a Schmitt trigger. EN - Enable The Enable pin is an active low enable function for all eight output drivers. When EN is high, drive from the Output Data Buffer is held low and all output drivers are disabled. When EN is low, the output drivers are enabled and data in the 8-bit shift register is transparent to the Output Data Buffer. This input has a Schmitt trigger. LGND and GND - Ground LGND is the logic input power supply ground pin. The GND pins are common grounds for the Power Output Drivers. The power supplies for the logic and power circuits require a common ground. To minimize ground bounce at the logic input, the external ground return path for the GND pin should be separate from the LGND pin. LGND and GND have common substrate ground connections on the chip. SO - Serial Data Out The Serial Data Out allows other ICs to be serially cascaded. For example, a 10-bit LED driver may be located behind the HIP0051. A controlling microprocessor may then clock out 18 bits of information and simultaneously strobe both parts. The cascaded ICs may be the same or different from the HIP0051. DR0 to DR7 - Outputs 0 Thru 7 The Drain Output pins of the DMOS Power Drivers are capable of sinking 250mA.
OUTPUT CONTROL TABLE STROBE D1 0 1 1 1 1 0 1 D2 0 0 1 1 1 0 1 8-BIT SERIAL DATA (LATCHED) D3 0 0 0 1 1 0 1 D4 0 0 0 0 1 0 1 D5 0 0 0 0 0 1 1 D6 0 0 0 0 0 1 1 D7 0 0 0 0 0 1 1 D8 0 0 0 0 0 1 1 DR1 OFF ON ON ON ON OFF ON DR2 OFF OFF ON ON ON OFF ON DR3 OFF OFF OFF ON ON OFF ON OUTPUT DR4 OFF OFF OFF OFF ON OFF ON DR5 OFF OFF OFF OFF OFF ON ON DR6 OFF OFF OFF OFF OFF ON ON DR7 OFF OFF OFF OFF OFF ON ON DR8 OFF OFF OFF OFF OFF ON ON
4
HIP0051 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
5

▲Up To Search▲

Price & Availability of HIP0051

	To Download HIP0051 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .